What Is the Best Way to Read in a Large Line of Data in Verilog
Lexical conventions in Verilog are like to C in the sense that information technology contains a stream of tokens. A lexical token may consist of one or more characters and tokens can exist comments, keywords, numbers, strings or white space. All lines should exist terminated by a semi-colon ;
.
Verilog is instance-sensitive, then var_a and var_A are different.
Comments
At that place are two ways to write comments in Verilog.
- A single line comment starts with
//
and tells Verilog compiler to care for everything afterwards this bespeak to the end of the line equally a comment. - A multiple-line annotate starts with
/*
and ends with*/
and cannot exist nested.
Even so, unmarried line comments can be nested in a multiple line annotate.
// This is a single line comment integer a; // Creates an int variable called a, and treats everything to the right of // as a comment /* This is a multiple-line or block comment */ /* This is /* an invalid nested block comment */ */ /* However, // this one is okay */ // This is also okay ///////////// Still okay
Whitespace
White space is a term used to stand for the characters for spaces, tabs, newlines and formfeeds, and is usually ignored by Verilog except when it separates tokens. In fact, this helps in the indentation of code to make it easier to read.
module dut; // 'module' is a keyword, // 'dut' is an identifier reg [viii*half-dozen:1] proper name = "Hello!"; // The 2 spaces in the starting time are ignored
All the same blanks(spaces) and tabs (from TAB central) are not ignored in strings. In the case beneath, the string variable called addr gets the value "Earth " because of preservation of spaces in strings.
// In that location is no space in the outset of this line, // merely there's a space in the string reg [8*6:one] addr = "Earth "; endmodule
Operators
In that location are three types of operators: unary, binary, and ternary or conditional.
- Unary operators shall appear to the left of their operand
- Binary operators shall announced betwixt their operands
- Provisional operators take 2 separate operators that separate three operands
x = ~y; // ~ is a unary operator, and y is the operand 10 = y | z; // | is a binary operator, where y and z are its operands 10 = (y > 5) ? w : z; // ?: is a ternary operator, and the expression (y>five), w and z are its operands
If the expression (y > five) is true, and so variable 10 will get the value in w, else the value in z.
Number Format
We are virtually familiar with numbers being represented equally decimals. Withal, numbers can also be represented in binary, octal and hexadecimal. By default, Verilog simulators treat numbers as decimals. In society to represent them in a different radix, sure rules accept to be followed.
xvi // Number xvi in decimal 0x10 // Number 16 in hexadecimal 10000 // Number xvi in binary 20 // Number 16 in octal
Sized
Sized numbers are represented as shown beneath, where size is written only in decimal to specify the number of $.25 in the number.
[size]'[base_format][number]
- base_format can be either decimal ('d or 'D), hexadecimal ('h or 'H) and octal ('o or 'O) and specifies what base the number office represents.
- number is specified as sequent digits from 0, one, 2 ... 9 for decimal base format and 0, ane, two .. ix, A, B, C, D, Due east, F for hexadecimal.
3'b010; // size is three, base format is binary ('b), and the number is 010 (indicates value 2 in binary) iii'd2; // size is 3, base format is decimal ('d) and the number is two (specified in decimals) 8'h70; // size is 8, base format is hexadecimal ('h) and the number is 0x70 (in hex) to represent decimal 112 9'h1FA; // size is 9, base format is hexadecimal ('h) and the number is 0x1FA (in hex) to represent decimal 506 iv'hA = 4'd10 = iv'b1010 = 4'o12 // Decimal x can exist represented in whatever of the four formats 8'd234 = 8'D234 // Legal to utilize either lower case or upper case for base format 32'hFACE_47B2; // Underscore (_) can be used to separate 16 bit numbers for readability
Uppercase letters are legal for number specification when the base format is hexadecimal.
16'hcafe; // lowercase messages Valid 16'hCAFE; // majuscule letters Valid 32'h1D40_CAFE; // underscore tin can be used equally separator between 4 letters Valid
Unsized
Numbers without a base_format specification are decimal numbers past default. Numbers without a size specification have a default number of bits depending on the type of simulator and machine.
integer a = 5423; // base format is not specified, a gets a decimal value of 5423 integer a = 'h1AD7; // size is non specified, because a is int (32 bits) value stored in a = 32'h0000_1AD7
Negative
Negative numbers are specified by placing a minus -
sign earlier the size of a number. It is illegal to have a minus sign betwixt base_format and number.
-6'd3; // 8-bit negative number stored as two'south complement of 3 -6'sd9; // For signed maths 8'd-4; // Illegal
Strings
A sequence of characters enclosed in a double quote " "
is chosen a string. Information technology cannot be split into multiple lines and every grapheme in the string take 1-byte to be stored.
"Hello Earth!" // String with 12 characters -> require 12 bytes "10 + z" // String with 5 characters "How are you feeling today ?" // Illegal for a cord to exist split into multiple lines
Identifiers
Identifiers are names of variables so that they tin can be referenced afterwards. They are made up of alphanumeric characters [a-z][A-Z][0-9]
, underscores _
or dollar sign $
and are case sensitive. They cannot start with a digit or a dollar sign.
integer var_a; // Identifier contains alphabets and underscore -> Valid integer $var_a; // Identifier starts with $ -> Invalid integer 5$ar_a; // Identifier contains alphabets and $ -> Valid integer 2var; // Identifier starts with a digit -> Invalid integer var23_g; // Identifier contains alphanumeric characters and underscore -> Valid integer 23; // Identifier contains only numbers -> Invalid
Keywords
Keywords are special identifiers reserved to ascertain the language constructs and are in lower example. A listing of important keywords is given below.
Verilog Revisions
Verilog has undergone a few revisions over the years and more additions have been made from 1995 to 2001 which is shown below.
Source: https://www.chipverify.com/verilog/verilog-syntax
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